1. Field of the Invention
The present invention relates in general to crosspoint switch arrays and in particular to a rapid switching crosspoint array providing implied disconnect and broadcast capabilities.
2. Description of Related Art
FIG. 1 illustrates a typical prior art crosspoint array 10 for selectively routing any of four input signals IN(0)-IN(3) to any of four output terminals OUT(0)-OUT(3). Crosspoint array 10 includes four xe2x80x9chorizontalxe2x80x9d input lines H(0)-H(3), four xe2x80x9cverticalxe2x80x9d output lines V(0)-V(3), and sixteen switch cells S(0,0)-S(3,3). Each switch cell S(M,N) can selectively provide a signal path between the Mth input line H(M) and the Nth output line V(N) depending on the state of a control bit an array controller 12 writes into a memory cell within the switch cell S(M,N). For example to route input signal IN(0) to output line OUT(2) controller 12 sets a bit in switch cell S(0,2) to a xe2x80x9ctruexe2x80x9d state so that the switch cell provides a signal path between input line H(0) and output line V(2). To thereafter break that signal path, controller 12 sets the bit in switch cell S(0,2) false.
Array controller 12 writes bits into the memory cells of the various switch cells S(M,N) in response to commands from an external host computer (not shown) requesting the controller to make or break particular routing paths through switch array 10. A separate pair of xe2x80x9cbit linesxe2x80x9d B(N) and B*(N) links controller 12 to the Nth column of switch cells S(0,N)-S(3,N), and a separate xe2x80x9crow addressxe2x80x9d line R(M) links controller 12 to each Mth row of switch cells S(M,0)-S(M,3). For example, to turn on switch cell S(0,0), controller 12 drives the cell""s B(0) bit line true, drives its B*(0) bit line false, and then pulses the R(0) line. To turn off switch cell S(0,0), controller 12 drives the B(0) line false, drives the B*(0) line true, and then pulses the R0 line. When controller 12 sets both of a cells bit lines false, the state of the cell""s control bit remains unchanged when controller 12 pulses its row address line. For example, when controller 12 is writing a bit only to cell S(0,0), it keeps bit lines B(1)-B(3) and B*(1)-B(3) low so that the bits in cells S(0,1)-S(0,3) remain unchanged when controller 12 pulses row address line R(0).
FIG. 2 illustrates a typical implementation of switch cell S(0,0) of array 10 of FIG. 1; other switch cells are similar. Switch cell S(0,0) includes an S/R flip-flop 14 for storing the control bit. The Q output of flip-flop 14 drives the gate of a complementary metal oxide silicon (CMOS) pass transistor 18 linking the H(0) and V(0) lines. When the Q output of flip-flop 14 is high transistor 18 makes a signal path between H(0) and V(0) and when the Q output is low transistor 18 breaks that signal path. A logic circuit 15, driving the set (S) and reset (R) inputs of flip-flop 14, decodes the R(0), B(0) and B*(0) lines to determine when to set or reset the flip-flop.
Broadcasting
Switch array 10 can xe2x80x9cbroadcastxe2x80x9d one input signal to more than one output line. For example, when control bits in all four switch cells S(0,N) of the top row are set true (where N=0 through 3) switch array 10 concurrently routes the IN(0) signal to all output terminals OUT(0)-OUT(3). Some controllers 12 can concurrently write control bits to all cells of a given row of switch cells at a time. For example to turn on all cells S(0,0)-S(0,3) of the top row at the same time so that input signal IN(0) is broadcast to every output terminal OUT(0)-OUT(3), controller 12 could drive all bit lines B(0)-B(3) true, drive all bit lines B*(0)-B*(0) false, and then pulse the R0 line. However to tell controller 12 how to set a bit in each cell S(M,N) along the Mth row, the controller""s input command would have to convey a relatively large amount of information. In the example switch array 10 of FIG. 1, where M=N=4, a command would have at least two bits to indicate which of four array rows is to be write addressed and eight bits to indicate how controller 12 should set each of the eight bit lines B(0)-B(3) and B*(0)-B*(3). Thus a command would have to be at least 10 bits wide. In a larger Mxc3x97N array, for example where M=N=512, such a command would have to include at least 1031 bits. Since 1031 bits would have to be applied serially to controlled 12, the time required to load such a command into the controller would substantially increase the time required for an external host computer to change signal brag routing through crosspoint array 10.
Some controllers 12 set control bits in only one switch cell at a time. Thus an input command to such a controller would reference the address of a single cell and indicate the state of its single control bit. Accordingly, an input command to a 512xc3x97512 controller 12 that only writes to one cell at a time would require 9 bits to identify the row of the cell, 9 bits to identify the column of the cell and one bit to specify the desired state of the cell""s control bit. Since such a command would be only require a total of 19 bits, it could be loaded into controller 12 much quicker than a 1031 bit command of an 512xc3x97512 array controller that writes to an entire row.
However when operating a crosspoint array in a broadcast mode, a controller that can write to only one cell at a time requires many write cycles to reconfigure the array to carry out a broadcast. For example suppose array 10 is broadcasting input signal IN(0) to all output terminals and the host computer wants to switch it so that it broadcasts input signal IN(1) to all output terminals. To do so, the host computer would have to command controller 12 to set the control bit in each of the four switch cells of row 0 false and to set the control bit in each of the four switch cells of row 1 true. This would require 8 write cycles. In a 512xc3x97512 array, such an operation would require 1024 write cycles. While all these write operations are taking place, switch 10 is in various intermediate states wherein it xe2x80x9cpartiallyxe2x80x9d broadcasts either the IN(0) and/or IN(1) signal. In many applications allowing the crosspoint array to exist in such intermediate states can be problematic.
Therefore what is needed is a crosspoint array and controller architecture that allows the controller to setup a broadcast in only a single write cycle in response to a short command.
In many applications, such as for example in network routing switches, input signals xe2x80x9ccompetexe2x80x9d for paths to output terminals. When one input signal is broadcast to all output terminals, all other traffic through the crosspoint array must temporarily stop because the input signal being broadcast ties up all the output terminals. To temporarily carry out a broadcast, a conventional controller 12 would first have to set the control bits in all cells of one array row true and set the control bits in all other cells false. To resume normal traffic after the broadcast is complete, controller 12 would have to reprogram the entire array 10 to the state it was in prior to the broadcast. Thus not only would the processes of setting up a temporary broadcast and then returning array 10 to its previous routing state require a large number of write operations, it would also require the host computer sending commands to controller 12 to remember the switching state of all switch cells prior to the broadcast so that it could return them to those states following the broadcast.
Therefore what is also needed is a large crosspoint switch that can quickly switch to broadcast a signal and then quickly return to its previous routing state without requiring an external host computer to remember what that previous routing state was.
Disconnecting
While it is possible for crosspoint array 10 to concurrently forward more than one of input signals IN(0)-IN(3) to the same one of output terminals OUT(0)-OUT(3), such a routing configuration is considered xe2x80x9cillegalxe2x80x9d in most applications. Hence while more than one switch cell S(M,N) of any given row M can be turned on at the same time to broadcast an input signal to several outputs, in most applications only one switch cell of any given column N is allowed to be turned on at the same time. Assume, for example, that switch S(1,1) is currently routing input signal IN(1) to output terminal OUT(1), and suppose that an external host computer wishes to reconfigure array 10 so that it routes input signal IN(3) to output terminal OUT(1). To do that the host computer must command controller 12 to first set the internal control bit of switch cell S(1,1) false so that it no longer provides a signal path for IN(1) to output terminal OUT(1). The host computer must then command controller 12 to set the bit in switch cell S(3,1) true so that array 10 will begin routing input signal IN(3) to output terminal OUT(1). One drawback to this operation is that it takes two commands and two write cycles to turn off cell S(1,1) and one to turn on cell S(3,1).
What is also needed is an improved crosspoint array wherein a single, relatively small input command can tell controller 12 to quickly switch from broadcasting one signal to broadcasting another.
An Nxc3x97M crosspoint switch in accordance with the invention routes input signals from any of N input terminals to one or more of M output terminals in response to control signals from a controller indicating desired signal paths between the input and output terminals. The crosspoint switch includes N drivers, M receivers, and a switch cell array having N rows and M columns of switch cells. Each of the N drivers buffers a separate one of the input signals arriving at an input terminal into the crosspoint switch array and each of the M receivers buffers an array output signal onto a separate one of the output terminals. Each switch cell of the crosspoint array includes a pass gate transistor for selectively making or breaking a signal path between one of the input terminals and one of the output terminals of the array in response to the control signals.
In accordance with one aspect of the invention, each switch cell includes a first memory cell for storing a data bit, a second memory cell for storing a control bit, and a logic circuit. The control bit sets the state of the switch cell""s transistor to make or break the signal path between the cell""s input line and the output line. The control signals can tell the logic circuit to set either the data bit or the control bit to a particular state and can tell the logic circuit to transfer the data bit from the first memory cell to the second memory cell.
In a normal mode of operation, to reconfigure the routing paths through the array, the controller writes data bits to first memory cells of one or more of the switch cells. It then signals the logic circuits of all switch cells to concurrently transfer the data bit from the first memory cell into the second memory cell, thereby reconfiguring the routing paths.
In a prior art crosspoint switch array, the process of reconfiguring the array""s routing paths takes place sequentially, with the controller making or breaking one path at a time. During the time required to sequentially reconfigure several routing paths, for example when switching between two large parallel buses, the prior art array passes through a series of undesirable intermediate routing states during which no transmissions can take place on any of the buses being switched. By initially sequentially writing all path configuration data into the first memory cells (which has no immediate effect on the array""s signal routing paths) and then concurrently transferring the routing data from all first memory cells to all second memory cells, the array of the present invention can quickly switch from one desired routing pattern to another without having to pass through any unwanted routing patterns.
In accordance with another aspect of the invention, the crosspoint switch includes an implied disconnect mode of operation. In the implied disconnect mode, whenever the control signals tell the logic circuit of any particular cell along an Mth column of the array to make a signal path to the Mth output terminal, each other cell of the Mth column currently providing a signal path to the Mth output terminal automatically breaks that signal path. This prevents the controller from having to use an additional write cycle to tell each other cell to break its signal path.
In accordance with a further aspect of the invention, the crosspoint switch also includes a broadcast mode of operation wherein the controller concurrently tells the logic circuits of all M cells along an Nth row of the array to form signal paths to all M outputs terminals so that the Nth input signal can be broadcast to all output terminals. The controller does this by telling the logic circuits of the Nth row to directly write to the second memory cell. This alters the control bit in the second memory cell to immediately create a signal path, but leaves the data bit in the first memory cell unchanged. At the same time, the logic circuits of all other switch cells set the control bits in their second memory cells to break their signal paths. Thus the array is quickly configured in one write cycle to carry out the broadcast operation. But, the first memory cells continue to store data defining the array""s prior routing pattern. Thereafter, the controller can restore the array to the prior signal routing pattern by signaling the logic circuit in all switch cells to transfer the data bits stored in all first memory cells into all second memory cells in a single write operation.
It is accordingly an object of the invention to provide a crosspoint switch that can rapidly switch between routing patterns without passing though intermediate patterns.
It is another object of the invention to provide a crosspoint switch capable of automatically disconnecting any existing path to an output terminal whenever making a new path to that output terminal.
It is accordingly a further object of the invention to provide a crosspoint switch capable of rapidly setting up a signal broadcast and thereafter quickly return to a previous routing pattern.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.